Memory Management(1) - Hardware Level

In this article, I will represent some concepts related to memory management from the perspective of hardware (specifically Intel 80386).

Most of the content comes from this document.

What I have done is to extract basic content and draw the relationship between concepts.

To understand the following article, you should keep in mind all the concepts mentioned below.

Page Traslation

The 80386 transforms logical addresses (i.e., addresses as viewed by programmers) into physical address (i.e., actual addresses in physical memory) in two steps:

  • Segment translation, in which a logical address (consisting of a
    segment selector and segment offset) are converted to a linear address.

  • Page translation, in which a linear address is converted to a physical
    address. This step is optional, at the discretion of systems-software designers.

Page translation is in effect only when the PG bit of CR0 is set.

This bit is typically set by the operating system during software initialization.

Page Frame (Page)

A page frame is a 4K-byte unit of contiguous addresses of physical memory. Pages begin onbyte boundaries and are fixed in size.

Page Frame Address

The page frame address specifies the physical starting address of a page.

Because pages are located on 4K boundaries, the low-order 12 bits are always zero.

Linear Address

A linear address refers indirectly to a physical address by specifying a page table, a page within that table, and an offset within that page.

31        22  21       12 11           0
 ---------------------------------------
|    DIR    |    PAGE    |    OFFSET    |
 ---------------------------------------

The addressing mechanism uses theDIR field as an index into a page directory,

uses the PAGE field as an index into the page table determined by the page directory, and

uses the OFFSET field to address a byte within the page determined by the page table.

Page Tables

A page table is simply an array of 32-bit page specifiers.

A page table is itself a page, and therefore contains 4 Kilobytes of memory or at most 1K 32-bit entries.

The physical address of the current page directory is stored in the CPU register CR3, also called the page directory base register (PDBR).

Page-Table Entries

Format of a Page Table Entry

31                         12 11                                      0
 ------------------------------------------------------------------------
| PAGE FRAME ADDRESS 31...12 | AVAIL | 0 0 | D | A | 0 0 | U/S | R/W | P |
 ------------------------------------------------------------------------

 P      - PRESENT
 R/W    - READ/WRITE
 U/S    - USER/SUPERVISOR
 A      - ACCESSED 
 D      - DIRTY
 AVAIL  - AVAILABLE FOR SYSTEMS PROGRAMMER USE

NOTE: 0 INDICATES INTEL RESERVED. DO NOT DEFINE.
  • Present Bit
    The Present bit indicates whether a page table entry can be used in address translation. P=1 indicates that the entry can be used.

  • Read/Write and User/Supervisor Bits
    These bits are not used for address translation, but are used for page-level protection.

  • Accessed and Dirty Bits
    The processor sets the corresponding accessed bits in both levels of page tables to 1 before a read or write operation to a page.

The processor sets the dirty bit in the second-level page table to 1 before a write to an address covered by that page table entry. The dirty bit in directory entries is undefined.

An operating system that supports paged virtual memory can use these bits to determine what pages to eliminate from physical memory when the demand for memory exceeds the physical memory available. The operating system is responsible for testing and clearing these bits.

Page Translation Cache

For greatest efficiency in address translation, the processor stores the most recently used page-table data in an on-chip cache.

operating-system programmers must flush the cache whenever the page tables are changed. The page-translation cache can be flushed by either of two methods:

1. By reloading CR3 with a MOV instruction; for example: MOV CR3, EAX
2. By performing a task switch to a TSS that has a different CR3 image than the current TSS. 

Mind mapping

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